1. Which of the following language can describe the hardware?.
A. C.
B. C++.
C. JAVA.
D. VHDL.
Answer= VHDL
2. What do VHDL stand for?.
A. Verilog hardware description language.
B. VHSIC hardware description language.
C. very hardware description language.
D. VMEbus description language.
Answer= VHSIC hardware description language
3. What does VHSIC stand for?.
A. very high speed integrated chip.
B. very high sensor integrated chip.
C. Verilog system integrated chip.
D. Verilog speed integrated chip.
Answer= very high speed integrated chip
4. Each unit to be modelled in a VHDL design is known as.
A. behavioural model.
B. design architecture.
C. design entity.
D. structural model.
Answer= design entity
5. Which of the following are capable of displaying output signal waveforms resulting from stimuli applied to the inputs?.
A. VHDL simulator.
B. VHDL emulator.
C. VHDL debugger.
D. VHDL locater.
Answer= VHDL simulator
6. Which of the following describes the connections between the entity port and the local component?.
A. port map.
B. one-to-one map.
C. many-to-one map.
D. one-to-many maps.
Answer= port map
7. Who proposed the CSA theory?.
A. Russell.
B. Jacome.
C. Hayes.
D. Ritchie.
Answer= Hayes
8. Which of the following is a systematic way of building up value sets?.
A. CSA theory.
B. Bayes theorem.
C. Russell's power mode;.
D. first power model.
Answer= CSA theory
9. Which of the following is an abstraction of the signal impedance?.
A. level.
B. strength.
C. size.
D. nature.
Answer= strength
10. Which of the following is an abstraction of the signal voltage?.
A. level.
B. strength.
C. nature.
D. size.
Answer= level
11. How many kinds of wait statements are available in the VHDL design?.
A. 3.
B. 4.
C. 5.
D. 6.
Answer= 4
12. Which wait statement does follow a condition?.
A. wait for.
B. wait until.
C. wait.
D. wait on.
Answer= wait until
13. Which wait statement does follow duration?.
A. wait for.
B. wait.
C. wait until.
D. wait on.
Answer= wait for
14. Which of the following is a C++ class library?.
A. C++.
B. C.
C. JAVA.
D. SystemC.
Answer= SystemC
15. Which model of SystemC uses floating point numbers to denote time?.
A. SystemC 1.0.
B. SystemC 2.0.
C. SystemC 3.0.
D. SystemC 4.0.
Answer= SystemC 1.0
16. Which model of SystemC uses the integer number to define time?.
A. SystemC 1.0.
B. SystemC 2.0.
C. SystemC 3.0.
D. SystemC 4.0.
Answer= SystemC 2.0
17. Which model of the SystemC helps in the communication purpose?.
A. SystemC 2.0.
B. SystemC 3.0.
C. SystemC 1.0.
D. SystemC 4.0.
Answer= SystemC 2.0
18. Which C++ class is similar to the hardware description language like VHDL?.
A. SystemC.
B. Verilog.
C. C.
D. JAVA.
Answer= SystemC
19. What does ESL stand for?.
A. EEPROM system level.
B. Electronic-system level.
C. Electrical system level.
D. Electron system level.
Answer= Electronic-system level
20. What to TLM stand for?.
A. transfer level modelling.
B. triode level modelling.
C. transaction level modelling.
D. transistor level modelling.
Answer= transaction level modelling
21. Which of the following is standardised as IEEE 1364?.
A. C.
B. C++.
C. FORTRAN.
D. Verilog.
Answer= Verilog
22. Who developed the Verilog?.
A. Moorby.
B. Thomas.
C. Russell and Ritchie.
D. Moorby and Thomson.
Answer= Moorby and Thomson
23. Which versions of the Verilog is known as System Verilog?.
A. Verilog version 3.0.
B. Verilog version 1.0.
C. Verilog version 1.5.
D. Verilog version 4.0.
Answer= Verilog version 3.0
24. Which of the following is a Verilog version 1.0?.
A. IEEE standard 1394-1995.
B. IEEE standard 1364-1995.
C. IEEE standard 1394-2001.
D. IEEE standard 1364-2001.
Answer= IEEE standard 1364-1995
25. Which of the following provides multiple-valued logic with eight signal strength?.
A. Verilog.
B. VHDL.
C. C.
D. C++.
Answer= Verilog
26. Which of the following is a superset of Verilog?.
A. Verilog.
B. VHDL.
C. System Verilog.
D. System VHDL.
Answer= System Verilog
27. Which hardware description language is more flexible?.
A. VHDL.
B. Verilog.
C. C.
D. C++.
Answer= VHDL
28. Which of the following provide more features for transistor-level descriptions?.
A. C++.
B. C.
C. VHDL.
D. Verilog.
Answer= Verilog
29. Which hardware description language is popular in the US?.
A. System Verilog.
B. System log.
C. Verilog.
D. VHDL.
Answer= Verilog
30. Which hardware description language is more popular in Europe?.
A. VHDL.
B. System log.
C. Verilog.
D. C.
Answer= VHDL
31. Which of the following is an analogue extension of the VHDL?.
A. VHDL-AMS.
B. System VHDL.
C. Verilog.
D. System Verilog.
Answer= VHDL-AMS
32. Which of the following support the modelling partial differentiation equation?.
A. gate level.
B. algorithmic level.
C. system level.
D. switch level.
Answer= system level
33. Which level simulates the algorithms that are used within the embedded systems?.
A. gate level.
B. circuit level.
C. switch level.
D. algorithmic level.
Answer= algorithmic level
34. Which level model components like ALU, memories registers, muxes and decoders?.
A. switch level.
B. register-transfer level.
C. gate level.
D. circuit level.
Answer= register-transfer level
35. Which of the following is the most frently used circuit-level model?.
A. SPICE.
B. VHDL.
C. Verilog.
D. System Verilog.
Answer= SPICE
36. Which model includes geometric information?.
A. switch-level model.
B. layout model.
C. gate level model.
D. register-transfer level.
Answer= layout model
37. Which model cannot simulate directly?.
A. circuit level model.
B. switch-level model.
C. gate level model.
D. layout model.
Answer= layout model
38. Which of the following models the components like resistors, capacitors etc?.
A. register-transfer level.
B. layout model.
C. circuit level model.
D. switch-level model.
Answer= circuit level model
39. Which model uses transistors as their basic components?.
A. switch model.
B. gate level.
C. circuit level.
D. layout model.
Answer= switch model
40. Which model is used to denote the boolean functions?.
A. switch level.
B. gate level model.
C. circuit level.
D. layout model.
Answer= gate level model
41. Which model is used for the power estimation?.
A. gate-level model.
B. layout model.
C. circuit model.
D. switch model.
Answer= gate-level model
42. In which model, the effect of instruction is simulated and their timing is not considered?.
A. gate-level model.
B. circuit model.
C. coarse-grained model.
D. layout model.
Answer= coarse-grained model
43. Which models communicate between the components?.
A. transaction level modelling.
B. fine-grained modelling.
C. coarse-grained modelling.
D. circuit level model.
Answer= transaction level modelling
44. Which of the following has a cycle-true set of simulation?.
A. switch-level model.
B. layout model.
C. circuit-level.
D. fine-grained model.
Answer= fine-grained model