Q1. The GAL16V8 has:.
A. 16 dedicated inputs..
B. 8 special function pins..
C. 8 pins that are used as inputs or outputs..
D. All of the above.
Answer= 8 pins that are used as inputs or outputs.
Q2. PALs tend to execute ________ logic..
A. SAP.
B. SOP.
C. PLA.
D. SPD.
Answer= SOP
Q3. How many pins are in an EDF10K70 package?.
A. 70.
B. 140.
C. 240.
D. 532.
Answer= 240
Q4. A GAL is essentially a ________..
A. non-reprogrammable PAL.
B. PAL that is programmed only by the manufacturer.
C. very large PAL.
D. reprogrammable PAL.
Answer= reprogrammable PAL
Q5. What is an OTP device?.
A. Optical transporting port.
B. Octal transmitting pixel.
C. Operational topical portable.
D. One-time programmable.
Answer= One-time programmable
Q6. How many product terms can a MAX+Plus II compiler borrow from adjacent macrocells in the same LAB?.
A. 0.
B. 5.
C. 10.
D. 20.
Answer= 5
Q7. Each programmable array logic (PAL) gate product is applied to an OR gate and, if combinational logic is desired, the product is ORed and then:.
A. the polarity fuse is restored.
B. sent to an inverter for output.
C. sent immediately to an output pin.
D. passed to the AND function for output.
Answer= sent to an inverter for output
Q8. ________ are used at the inputs of PAL/GAL devices in order to prevent input loading from a large number of AND gates..
A. Simplified AND gates.
B. Fuses.
C. Buffers.
D. Latches.
Answer= Buffers
Q9. A(n) ________ consists of a programmable array of AND gates that connects to a fixed array of OR gates and is usually OTP..
A. GAL.
B. CPLD.
C. PAL.
D. SPLD.
Answer= PAL
Q10. What is another name for digital circuitry called seQntial logic?.
A. logic macrocell.
B. logic array.
C. flip-flop memory circuitry.
D. inverter.
Answer= flip-flop memory circuitry
Q11. When did the first PLD appear?.
A. More than 10 years ago.
B. More than 20 years ago.
C. More than 30 years ago.
D. More than 40 years ago.
Answer= More than 30 years ago
Q12. PLDs, CPLDs, and FPGAs are all which type of device?.
A. PAL.
B. PLD.
C. EPROM.
D. SRAM.
Answer= PLD
Q13. Cascade chains are closely associated with ________..
A. CLBs.
B. SOP functions.
C. logic expansion.
D. all of the above.
Answer= all of the above
Q14. FPLA is:.
A. a nonmemory programmable device..
B. a programmable AND array..
C. a programmable OR array..
D. All of the above.
Answer= All of the above
Q15. A(n) ________ is a section of embedded logic that is commonly found in FPGAs..
A. LUT.
B. core.
C. DSP.
D. PI.
Answer= core
Q16. In a FLEX10K, what two outputs will the LE produce?.
A. The LAB and the fast track.
B. ON and OFF.
C. Hi-Z and ON.
D. Hi-Z and OFF.
Answer= The LAB and the fast track
Q17. ASIC stands for:.
A. advanced speed integrated circuit..
B. advanced standard integrated circuit..
C. application specific integrated circuit..
D. application speedy integrated circuit..
Answer= application specific integrated circuit.
Q18. The final step in the device programming seQnce is ________..
A. compiling.
B. downloading.
C. simulation.
D. synthesis.
Answer= downloading
Q19. Most look-up tables in field-programmable gate arrays (FGPAs) use ________ inputs, resulting in ________ possible outputs..
A. 4,16.
B. 8,16.
C. 4,12.
D. 6,12.
Answer= 4,16
Q20. What is the defining difference between microprocessor/DSP systems and other digital systems?.
A. The digital system follows a programmed seQnce of instructions that the designer specified..
B. The microprocessor follows a programmed seQnce of instructions that the designer specified..
C. The digital system is faster..
D. The microprocessor/DSP is faster..
Answer= The digital system follows a programmed seQnce of instructions that the designer specified.
Q21. Why have PLDs taken over so much of the market?.
A. One PLD does the work of many ICs..
B. The PLDs are cheaper..
C. Less power is required..
D. All of the above.
Answer= All of the above
Q22. CLB is the acronym for ________..
A. Configurable Logic Block.
B. Configurable Logic Buffer.
C. Critical Logic Buffer.
D. Constant Logic Buffer.
Answer= Configurable Logic Block
Q23. What can the GAL22V10 do that the GAL16V8 cannot?.
A. It has an extra-large array..
B. It is in-system programmable..
C. It has twice the special function pins..
D. All of the above.
Answer= It is in-system programmable.
Q24. A circuit that implements a combinational logic function by storing a list of output values that correspond to all possible input combinations is a(n) ________..
A. output logic macrocell.
B. look-up table.
C. parallel logic expander.
D. logic element.
Answer= look-up table
Q25. By adding an OR gate to a simple programmable logic device (SPLD) the foundation for a(n) ________ is made possible..
A. PAL.
B. PLA.
C. CPLD.
D. EEPROM.
Answer= PAL
Q26. What does the Altera FLEX10K PLD use in place of AND and OR arrays?.
A. Nothing, it uses AND and OR arrays..
B. Look-up tables.
C. SRAM-based memory.
D. HPLD architecture.
Answer= Look-up tables
Q27. PIA is an acronym for ________..
A. Programmable Interface Array.
B. Post Integrated Array.
C. Programmable Input Array.
D. Programmable Interconnect Array.
Answer= Programmable Interconnect Array
Q28. Which one of the following is an embedded function of the Stratix II FPGA?.
A. AND-OR logic.
B. Programmable SOP.
C. Digital signal processing.
D. None of the above.
Answer= Digital signal processing
Q29. In an OLMC, where does the FMUX signal go?.
A. OMUX.
B. D flip-flop.
C. Matrix.
D. PAL.
Answer= Matrix
Q30. Which of the following testing procedures has one or more external moving parts?.
A. Bed-of-nails.
B. Flying probe.
C. EXTEST.
D. Boundary scan.
Answer= Flying probe
Q31. Field-programmable gate arrays (FGPAs) use ________ memory technology, which is ________..
A. DRAM, nonvolatile.
B. SRAM, nonvolatile.
C. SRAM, volatile.
D. RAM, volatile.
Answer= SRAM, volatile
Q32. A PAL16L8 has:.
A. 10 inputs and 8 outputs..
B. 8 inputs and 8 outputs..
C. 16 inputs and 16 outputs..
D. 16 inputs and 8 outputs..
Answer= 10 inputs and 8 outputs.
Q33. Now many times can a GAL be erased and reprogrammed?.
A. 0.
B. At least 100.
C. At least 1000.
D. Over 10,000.
Answer= At least 100
Q34. MPGA stands for:.
A. mass produced gated array..
B. Morgan-Phillips gated array..
C. memory programmed ROM..
D. mask programmed ROM..
Answer= mask programmed ROM.
Q35. Which of the following increases the number of product terms by borrowing unused product from other macrocells?.
A. Shared expander.
B. Parallel expander.
C. Series expander.
D. Slice expander.
Answer= Parallel expander
Q36. Which is a mode of operation of the GAL16V8?.
A. Simple mode.
B. Complex mode.
C. Registered mode.
D. All of the above.
Answer= All of the above
Q37. Which of the following testing procedures uses the JTAG IEEE standard?.
A. Bed-of-nails.
B. Flying probe.
C. EXTEST.
D. Boundary scan.
Answer= Boundary scan
Q38. The macrocells in a PAL/GAL are located ________..
A. after the programmable AND arrays.
B. ahead of the programmable AND arrays.
C. at the input terminals.
D. at the output terminals.
Answer= after the programmable AND arrays
Q39. The content of a simple programmable logic device (PLD) consists of:.
A. fuse-link arrays.
B. thousands of basic logic gates.
C. advanced seQntial logic functions.
D. thousands of basic logic gates and advanced seQntial logic functions.
Answer= thousands of basic logic gates and advanced seQntial logic functions
Q40. Which is a major digital system category?.
A. Standard logic devices.
B. ASICs.
C. Microprocessor/DSP devices.
D. All of the above.
Answer= All of the above
Q41. What is the input/output pin configuration of the GAL22V10?.
A. 10 output pins and 12 input pins.
B. 2 special-purpose pins.
C. 8 pins that are either inputs or outputs.
D. All of the above.
Answer= 10 output pins and 12 input pins
Q42. What does a dot mean when placed on a PLD circuit diagram?.
A. A point that is programmable.
B. A point that cannot change.
C. An intersection of logic blocks.
D. An input or output point.
Answer= A point that cannot change
Q43. FPGA is the acronym for ________..
A. Flexible Programming [of] Generic Assemblies.
B. Field Programmable Generic Array.
C. Field Programmable Gate Array.
D. Field Programmer's Gate Assembly.
Answer= Field Programmable Gate Array
Q44. How many combinations are handled in an LUT?.
A. 4.
B. 8.
C. 16.
D. 32.
Answer= 16
Q45. Which of the following is true?.
A. Altera uses PAL architecture and Xilinx uses PLA architecture..
B. Altera uses PLA architecture and Xilinx uses PAL architecture..
C. Altera and Xilinx both use PAL architecture..
D. Altera and Xilinx both use PLA architecture..
Answer= Altera uses PAL architecture and Xilinx uses PLA architecture.
Q46. What is the status of a tristate output buffer on a MAX7000S family device?.
A. It is permanently enabled or disabled..
B. It is controlled by one of the two global output enable pins..
C. It is controlled by other inputs or functions generated by other macrocells..
D. All of the above.
Answer= All of the above
Q47. GAL is an acronym for ________..
A. Generic Array Logic.
B. General Array Logic.
C. Giant Array Logic.
D. Generic Analysis Logic.
Answer= Generic Array Logic
Q48. What gives a GAL its flexibility?.
A. Its speed.
B. Its reprogrammable EPROM.
C. Its large logic arrays.
D. Its programmable OLMCs.
Answer= Its programmable OLMCs
Q49. What programmable technology is used in FPGA devices?.
A. SRAM.
B. FLASH.
C. Antifuse.
D. All of the above.
Answer= All of the above
Q50. What is an EPM7128S?.
A. An Altera MAX7000S CPLD.
B. An Altera UP2.
C. A DeVry eSOC.
D. A BSR PL DT-2.
Answer= An Altera MAX7000S CPLD
Q51. An SPLD listed as 22V10 has ________..
A. 10 inputs, 10 outputs, and requires a 22 V power source.
B. 11 inputs, 11 outputs, and requires a 10 V power source.
C. 22 inputs and 10 outputs.
D. 10 inputs and 22 outputs.
Answer= 22 inputs and 10 outputs
Q52. The Altera MAX 7000 series ________..
A. uses an E2PROM process technology.
B. can have between 2 and 16 LABS and I/O control blocks.
C. is available with DC supply voltages between 2.5 V and 5 V.
D. all of the above.
Answer= all of the above
Q53. A macrocell basically contains ________..
A. a programmable AND-OR gate array and some input buffers.
B. an OR-gate array and some output logic.
C. an AND-OR gate array and some output logic.
D. licensed programming.
Answer= an OR-gate array and some output logic
Q54. The complex programmable logic device (CPLD) features a(n) ________ type of memory..
A. volatile.
B. nonvolatile.
C. EPROM.
D. volitile EPROM.
Answer= nonvolatile
Q55. How many macrocells are in a MAX700S LAB?.
A. 8.
B. 16.
C. 32.
D. 64.
Answer= 16
Q56. Which is not a type of PLD?.
A. SPLD.
B. HPLD.
C. CPLD.
D. FPGA.
Answer= HPLD
Q57. An SPLD listed as 16H8 would have ________..
A. active-HIGH outputs.
B. active-LOW outputs.
C. variable-level outputs.
D. latches at the outputs.
Answer= active-HIGH outputs
Q58. Which type of PLD could be used to program basic logic functions?.
A. PLA.
B. PAL.
C. CPLD.
D. all the above.
Answer= all the above
Q59. The complex programmable logic device (CPLD) contains several PAL-type simple programmable logic devices (SPLDs) called:.
A. macrocells.
B. microcells.
C. AND/OR arrays.
D. fuse-link arrays.
Answer= macrocells
Q60. Which is not a part of a GAL16V8's OLMC?.
A. TSMUX.
B. OMUX.
C. FMUX.
D. PSMUX.
Answer= PSMUX
Q61. What is PROM?.
A. SPLD.
B. QPLD.
C. HPLD.
D. PLD.
Answer= PLD
Q62. A slice consists of ________..
A. only two logic cells.
B. between 2 and 8 logic cells.
C. up to 16 logic cells.
D. a single CLB.
Answer= only two logic cells
Q63. Product terms are the outputs of which type of gate within a PLD array?.
A. OR.
B. XOR.
C. AND.
D. flip-flop.
Answer= AND
Q64. If an analog signal is to be converted to an 8-bit resolution, how many comparators are used in a parallel-encoded ADC?.
A. 127.
B. 128.
C. 255.
D. 256.
Answer= 256
Q65. A transducer is a device that:.
A. converts a physical variable to an electrical variable.
B. converts analog data to meaningful data.
C. controls a physical variable.
D. stores digital data and then processes that data according to a set of specified instructions.
Answer= converts a physical variable to an electrical variable