1. Which is the most basic non-volatile memory?.
A. Flash memory.
B. PROM.
C. EPROM.
D. ROM.
Answer= ROM
2. Who has invented flash memory?.
A. Dr.Fujio Masuoka.
B. John Ellis.
C. Josh Fisher.
D. John Ruttenberg.
Answer= Dr.Fujio Masuoka
3. Which of the following is serial access memory?.
A. RAM.
B. Flash memory.
C. Shifters.
D. ROM.
Answer= Shifters
4. Which is the early form of non-volatile memory?.
A. magnetic core memory.
B. ferrimagnetic memory.
C. anti-magnetic memory.
D. anti-ferromagnetic.
Answer= magnetic core memory
5. Which of the following memories has more speed in accessing data?.
A. SRAM.
B. DRAM.
C. EPROM.
D. EEPROM.
Answer= SRAM
6. In which memory, the signals are multiplexed?.
A. DRAM.
B. SRAM.
C. EPROM.
D. EEPROM.
Answer= DRAM
7. How many main signals are used with memory chips?.
A. 2.
B. 4.
C. 6.
D. 8.
Answer= 4
8. What is the purpose of the address bus?.
A. to provide data to and from the chip.
B. to select a specified chip.
C. to select a location within the memory chip.
D. to select a read/write cycle.
Answer= to select a location within the memory chip
9. Which are the two main types of processor connection to the motherboard?.
A. sockets and slots.
B. sockets and pins.
C. slots and pins.
D. pins and ports.
Answer= sockets and slots
10. Which of the following has programmable hardware?.
A. microcontroller.
B. microprocessor.
C. coprocessor.
D. FPGA.
Answer= FPGA
11. Who invented TriMedia processor?.
A. Intel.
B. IBM.
C. Apple.
D. NXP Semiconductor.
Answer= NXP Semiconductor
12. Why is SRAM more preferably in non-volatile memory?.
A. low-cost.
B. high-cost.
C. low power consumption.
D. transistor as a storage element.
Answer= low power consumption
13. Which of the following ahs refreshes control mechanism?.
A. DRAM.
B. SRAM.
C. Battery backed-up SRAM.
D. Pseudo-static RAM.
Answer= Pseudo-static RAM
14. Which storage element is used by MAC and IBM PC?.
A. CMOS.
B. Transistor.
C. Capacitor.
D. Inductor.
Answer= CMOS
15. Which type of storage element of SRAM is very fast in accessing data but consumes lots of power?.
A. TTL.
B. CMOS.
C. NAND.
D. NOR.
Answer= TTL
16. What is approximate data access time of SRAM?.
A. 4ns.
B. 10ns.
C. 2ns.
D. 60ns.
Answer= 4ns
17. Who proposed the miniature card format?.
A. Intel.
B. IBM.
C. MIPS.
D. Apple.
Answer= Intel
18. How many MOSFETs are required for SRAM?.
A. 2.
B. 4.
C. 6.
D. 8.
Answer= 6
19. Which of the following is an SRAM?.
A. 1T-RAM.
B. PROM.
C. EEPROM.
D. EPROM.
Answer= 1T-RAM
20. Which of the following can access data even when the power supply is lost?.
A. Non-volatile SRAM.
B. DRAM.
C. SRAM.
D. RAM.
Answer= Non-volatile SRAM
21. Which of the following can easily convert to a non-volatile memory?.
A. SRAM.
B. DRAM.
C. DDR SRAM.
D. Asynchronous DRAM.
Answer= SRAM
22. Which memory storage is widely used in PCs and Embedded Systems?.
A. SRAM.
B. DRAM.
C. Flash memory.
D. EEPROM.
Answer= DRAM
23. Which of the following memory technology is highly denser?.
A. DRAM.
B. SRAM.
C. EPROM.
D. Flash memory.
Answer= DRAM
24. Which is the storage element in DRAM?.
A. inductor.
B. capacitor.
C. resistor.
D. mosfet.
Answer= capacitor
25. Which one of the following is a storage element in SRAM?.
A. capacitor.
B. inductor.
C. transistor.
D. resistor.
Answer= transistor
26. Which of the following is more volatile?.
A. SRAM.
B. DRAM.
C. ROM.
D. RAM.
Answer= DRAM
27. What is the size of a trench capacitor in DRAM?.
A. 1 Mb.
B. 4-256 Mb.
C. 8-128 Mb.
D. 64-128 Mb.
Answer= 4-256 Mb
28. Which of the following capacitor can store more data in DRAM?.
A. planar capacitor.
B. trench capacitor.
C. stacked-cell.
D. non-polar capacitor.
Answer= stacked-cell
29. In which of the memories, does the data disappear?.
A. SRAM.
B. DRAM.
C. Flash memory.
D. EPROM.
Answer= DRAM
30. Which of the following is the main factor which determines the memory capacity?.
A. number of transistors.
B. number of capacitors.
C. size of the transistor.
D. size of the capacitor.
Answer= number of transistors
31. What does VRAM stand for?.
A. video RAM.
B. verilog RAM.
C. virtual RAM.
D. volatile RAM.
Answer= video RAM
32. What does TCR stand for?.
A. temperature-compensated refresh.
B. temperature-compensated recovery.
C. texas CAS-RAS.
D. temperature CAS-RAS.
Answer= temperature-compensated refresh
33. How many data lines does 256*4 have?.
A. 256.
B. 8.
C. 4.
D. 32.
Answer= 4
34. How is the number of chips required is determined?.
A. number of data lines.
B. the minimum number of data.
C. width of the data path from the processor.
D. number of data lines and the width of the data path from the processor.
Answer= number of data lines and the width of the data path from the processor
35. Where is memory address stored in a C program?.
A. stack.
B. pointer.
C. register.
D. accumulator.
Answer= pointer
36. Which is the term that is used to refer the order of bytes?.
A. endianness.
B. memory organisation.
C. bit.
D. register.
Answer= endianness
37. Which of the following processors uses big endian representation?.
A. 8086.
B. ARM.
C. PowerPC.
D. Zilog Z80.
Answer= PowerPC
38. Which statement is true for a cache memory?.
A. memory unit which communicates directly with the CPU.
B. provides backup storage.
C. a very high-speed memory to increase the speed of the processor.
D. secondary storage.
Answer= a very high-speed memory to increase the speed of the processor
39. Which of the following memory organisation have the entire memory available to the processor at all times?.
A. segmented addressing.
B. paging.
C. virtual address.
D. linear address.
Answer= linear address
40. How many memory locations can be accessed by 8086?.
A. 1 M.
B. 2 M.
C. 3 M.
D. 4 M.
Answer= 1 M
41. Which of them is a memory that is allocated to the program in LIFO pattern?.
A. stack.
B. index.
C. accumulator.
D. base.
Answer= stack
42. What does SIMM stand for?.
A. single in-line memory module.
B. single interrupt memory module.
C. single information memory module.
D. same-in-line memory module.
Answer= single in-line memory module
43. Which of the memory organisation is widely used in parity bit?.
A. by 1 organisation.
B. by 4 organisation.
C. by 8 organisation.
D. by 9 organisation.
Answer= by 1 organisation
44. Which configuration of memory organisation replaces By 1 organisation?.
A. by 4 organisation.
B. by 8 organisation.
C. by 9 organisation.
D. by 16 organisation.
Answer= by 4 organisation
45. Which shifting helps in finding the physical address in 8086?.
A. shifting the segment by 8.
B. shifting the segment by 6.
C. shifting the segment by 4.
D. shifting the segment by 2.
Answer= shifting the segment by 4
46. Which memory organisation is supported in wider memories?.
A. by 8 organisation.
B. by 16 organisation.
C. by 9 organisation.
D. by 4 organisation.
Answer= by 16 organisation
47. Which of the following is a plastic package used primarily for DRAM?.
A. SIMM.
B. DIMM.
C. Zig-zag.
D. Dual-in-line.
Answer= Zig-zag
48. Which of the following have a 16 Mbytes addressed range?.
A. PowerPC.
B. M68000.
C. DSP56000.
D. TMS 320.
Answer= M68000
49. Which of the following can destroy the accuracy in the algorithms?.
A. delays.
B. error signal.
C. interrupt.
D. mmu.
Answer= delays
50. How many numbers of ways are possible for allocating the memory to the modular blocks?.
A. 1.
B. 2.
C. 3.
D. 4.
Answer= 3
51. Which of the following is replaced with the absolute addressing mode?.
A. relative addressing mode.
B. protective addressing mode.
C. virtual addressing mode.
D. temporary addressing mode.
Answer= relative addressing mode
52. What is the main purpose of the memory management unit?.
A. address translation.
B. large storage.
C. reduce the size.
D. provides address space.
Answer= address translation
53. Which of the following provides stability to the multitasking system?.
A. memory.
B. DRAM.
C. SRAM.
D. Memory partitioning.
Answer= Memory partitioning
54. Which of the following is used by the M68000 family?.
A. M68000.
B. 80386.
C. 8086.
D. 80286.
Answer= M68000
55. What can be done for the fine grain protection of the processor?.
A. add extra description bit.
B. add error signal.
C. add wait stage.
D. remains unchanged.
Answer= add extra description bit
56. Which of the following techni is used by the UNIX operating system?.
A. logical address memory.
B. physical address memory.
C. virtual memory techni.
D. translational address.
Answer= virtual memory techni
57. Which of the following consist two lines of legs on both sides of a plastic or ceramic body?.
A. SIMM.
B. DIMM.
C. Zig-zag.
D. Dual in-line.
Answer= Dual in-line
58. Which package has high memory speed and change in the supply?.
A. DIP.
B. SIMM.
C. DIMM.
D. zig-zag.
Answer= DIMM
59. Which is a subassembly package?.
A. dual-in-line.
B. zig-zag.
C. simm.
D. ceramic shell.
Answer= simm
60. What is the required voltage of DIMM?.
A. 2V.
B. 2.2V.
C. 5V.
D. 3.3V.
Answer= 3.3V
61. Which memory package has a single row of pins?.
A. SIMM.
B. DIP.
C. SIP.
D. zig-zag.
Answer= SIP
62. What is the access time of MCM51000AP10?.
A. 100ns.
B. 80ns.
C. 60ns.
D. 40ns.
Answer= 100ns
63. Which is the very basic techni of refreshing DRAM?.
A. refresh cycle.
B. burst refresh.
C. distributive refresh.
D. software refresh.
Answer= refresh cycle
64. How is the refresh rate calculated?.
A. by refresh time.
B. by the refresh cycle.
C. by refresh cycle and refresh time.
D. refresh frency and refresh cycle.
Answer= by refresh cycle and refresh time
65. Which is the commonly used refresh rate?.
A. 125 microseconds.
B. 120 microseconds.
C. 130 microseconds.
D. 135 microseconds.
Answer= 125 microseconds
66. How can we calculate the length of the refresh cycle?.
A. twice of normal access.
B. thrice of normal access.
C. five times of normal access.
D. six times of normal access.
Answer= twice of normal access
67. What type of error occurs in the refresh cycle of the DRAM?.
A. errors in data.
B. power loss.
C. timing issues.
D. not accessing data.
Answer= timing issues
68. What is the worst case delay of the burst refresh in 4M by 1 DRAM?.
A. 0.4ms.
B. 0.2ms.
C. 170ns.
D. 180ns.
Answer= 0.2ms
69. Which refresh technis depends on the size of time critical code for calculating the refresh cycle?.
A. burst refresh.
B. distributed refresh.
C. refresh cycle.
D. software refresh.
Answer= distributed refresh
70. Which of the following uses a timer for refresh techni?.
A. RAS.
B. CBR.
C. software refresh.
D. CAS.
Answer= software refresh
71. What is the main disadvantage in the software refresh of the DRAM?.
A. timer.
B. delay.
C. programming delay.
D. debugging.
Answer= debugging
72. Which refresh techni is useful for low power consumption?.
A. Software refresh.
B. CBR.
C. RAS.
D. Burst refresh.
Answer= CBR
73. Which refreshing technis generate a recycled address?.
A. RAS.
B. CBR.
C. Distributed refresh.
D. Software refresh.
Answer= RAS
74. Which of the following uses a software refresh in the DRAM?.
A. 8086.
B. 80386.
C. Pentium.
D. Apple II personal computer.
Answer= Apple II personal computer
75. How do CBR works?.
A. by asserting CAS before RAS.
B. by asserting CAS after RAS.
C. by asserting RAS before CAS.
D. by asserting CAS only.
Answer= by asserting CAS before RAS
76. Which of the refresh circuit is similar to CBR?.
A. software refresh.
B. hidden refresh.
C. burst refresh.
D. distribute refresh.
Answer= hidden refresh
77. Which technology is standardized in DRAM for determining the maximum time interval between the refresh cycle?.
A. IEEE.
B. RAPID.
C. JEDEC.
D. UNESCO.
Answer= JEDEC
78. In which pin does the data appear in the basic DRAM interfacing?.
A. dout pin.
B. din pin.
C. clock.
D. interrupt pin.
Answer= dout pin
79. What is the duration for memory refresh to remain compatible?.
A. 20 microseconds.
B. 12 microseconds.
C. 15 microseconds.
D. 10 microseconds.
Answer= 15 microseconds
80. Which interfacing method lowers the speed of the processor?.
A. basic DRAM interface.
B. page mode interface.
C. page interleaving.
D. burst mode interface.
Answer= basic DRAM interface
81. What is EDO RAM?.
A. extreme data operation.
B. extended direct operation.
C. extended data out.
D. extended DRAM out.
Answer= extended data out
82. What is RDRAM?.
A. refresh DRAM.
B. recycle DRAM.
C. Rambus DRAM.
D. refreshing DRAM.
Answer= Rambus DRAM
83. Which of the following can transfer up to 1.6 billion bytes per second?.
A. DRAM.
B. RDRAM.
C. EDO RAM.
D. SDRAM.
Answer= RDRAM
84. Which of the following cycle is larger than the access time?.
A. write cycle.
B. set up time.
C. read cycle.
D. hold time.
Answer= read cycle
85. Which mode of operation selects an internal page of memory in the DRAM interfacing?.
A. page interleaving.
B. page mode.
C. burst mode.
D. EDO RAM.
Answer= page mode
86. What is the maximum time that the RAS signal can be asserted in the page mode operation?.
A. 5 microseconds.
B. 10 microseconds.
C. 15 microseconds.
D. 20 microseconds.
Answer= 10 microseconds
87. Which of the following mode of operation in the DRAM interfacing has a page boundary?.
A. burst mode.
B. EDO RAM.
C. page mode.
D. page interleaving.
Answer= page mode
88. Which mode offers the banking of memory in the DRAM interfacing techni?.
A. page mode.
B. basic DRAM interfacing.
C. page interleaving.
D. burst mode.
Answer= page interleaving
89. Which of the following has a fast page mode RAM?.
A. burst mode.
B. page interleaving.
C. EDO memory.
D. page mode.
Answer= EDO memory
90. Which mode reduces the need for fast static RAMs?.
A. page mode.
B. page interleaving.
C. burst mode.
D. EDO memory.
Answer= burst mode
91. Which of the following is also known as hyper page mode enabled DRAM?.
A. page mode.
B. EDO DRAM.
C. burst EDO DRAM.
D. page interleaving.
Answer= EDO DRAM
92. What does BEDO DRAM stand for?.
A. burst EDO DRAM.
B. buffer EDO DRAM.
C. BIBO EDO DRAM.
D. bilateral EDO DRAM.
Answer= burst EDO DRAM
93. Which of the following is more quickly accessed?.
A. RAM.
B. Cache memory.
C. DRAM.
D. SRAM.
Answer= Cache memory
94. Which factor determines the effectiveness of the cache?.
A. hit rate.
B. refresh cycle.
C. refresh rate.
D. refresh time.
Answer= hit rate
95. Which of the following determines a high hit rate of the cache memory?.
A. size of the cache.
B. number of caches.
C. size of the RAM.
D. cache access.
Answer= size of the cache
96. Which of the following is a common cache?.
A. DIMM.
B. SIMM.
C. TLB.
D. Cache.
Answer= TLB
97. Which factor determines the number of cache entries?.
A. set commutativity.
B. set associativity.
C. size of the cache.
D. number of caches.
Answer= set associativity
98. What is the size of the cache for an 8086 processor?.
A. 64 Kb.
B. 128 Kb.
C. 32 Kb.
D. 16 Kb.
Answer= 64 Kb
99. How many possibilities of mapping does a direct mapped cache have?.
A. 1.
B. 2.
C. 3.
D. 4.
Answer= 1
100. Which of the following allows speculative execution?.
A. 12-way set associative cache.
B. 8-way set associative cache.
C. direct mapped cache.
D. 4-way set associative cache.
Answer= direct mapped cache
101. Which of the following refers to the number of consecutive bytes which are associated with each cache entry?.
A. cache size.
B. associative set.
C. cache line.
D. cache word.
Answer= cache line
102. Which factor determines the cache performance?.
A. software.
B. peripheral.
C. input.
D. output.
Answer= software
103. What are the basic elements required for cache operation?.
A. memory array, multivibrator, counter.
B. memory array, comparator, counter.
C. memory array, trigger circuit, a comparator.
D. memory array, comparator, CPU.
Answer= memory array, comparator, counter
104. How many divisions are possible in the cache memory based on the tag or index address?.
A. 3.
B. 2.
C. 4.
D. 5.
Answer= 4
105. What does DMA stand for?.
A. direct memory access.
B. direct main access.
C. data main access.
D. data memory address.
Answer= direct memory access
106. Which of the following cache has a separate comparator for each entry?.
A. direct mapped cache.
B. fully associative cache.
C. 2-way associative cache.
D. 16-way associative cache.
Answer= fully associative cache
107. What is the disadvantage of a fully associative cache?.
A. hardware.
B. software.
C. memory.
D. peripherals.
Answer= hardware
108. How many comparators present in the direct mapping cache?.
A. 3.
B. 2.
C. 1.
D. 4.
Answer= 1
109. Which mapping of cache is inefficient in software viewpoint?.
A. fully associative.
B. 2 way associative.
C. 16 way associative.
D. direct mapping.
Answer= direct mapping
110. Which mechanism splits the external memory storage into memory pages?.
A. index mechanism.
B. burst mode.
C. distributive mode.
D. a software mechanism.
Answer= index mechanism
111. Which of the following cache mapping can prevent bus thrashing?.
A. fully associative.
B. direct mapping.
C. n way set associative.
D. 2 way associative.
Answer= n way set associative
112. Which cache mapping have a sential execution?.
A. direct mapping.
B. fully associative.
C. n way set associative.
D. burst fill.
Answer= burst fill
113. Which address is used for a tag?.
A. memory address.
B. logical address.
C. cache address.
D. location address.
Answer= logical address
114. In which of the following the data is preserved within the cache?.
A. logical cache.
B. physical cache.
C. unified cache.
D. harvard cache.
Answer= physical cache
115. What is the disadvantage of the physical address?.
A. debugging.
B. delay.
C. data preservation.
D. data cleared.
Answer= delay
116. Which cache memory solve the cache coherency problem?.
A. physical cache.
B. logical cache.
C. unified cache.
D. harvard cache.
Answer= physical cache
117. What type of cache is used in the Intel 80486DX?.
A. logical.
B. physical.
C. harvard.
D. unified.
Answer= unified
118. Which of the following has a separate cache for the data and instructions?.
A. unified.
B. harvard.
C. logical.
D. physical.
Answer= harvard
119. Which type of cache is used the SPARC architecture?.
A. unified.
B. harvard.
C. logical.
D. physical.
Answer= logical
120. Which of the following approach uses more silicon area?.
A. unified.
B. harvard.
C. logical.
D. physical.
Answer= harvard
121. Which of the following include special address generation and data latches?.
A. burst interface.
B. peripheral interface.
C. dma.
D. input-output interfacing.
Answer= burst interface
122. Which of the following makes use of the burst fill techni?.
A. burst interfaces.
B. dma.
C. peripheral interfaces.
D. input-output interfaces.
Answer= burst interfaces
123. How did burst interfaces access faster memory?.
A. segmentation.
B. dma.
C. static column memory.
D. memory.
Answer= static column memory
124. Which of the following memory access can reduce the clock cycles?.
A. bus interfacing.
B. burst interfacing.
C. dma.
D. dram.
Answer= burst interfacing
125. How many clocks are required for the first access in the burst interface?.
A. 1.
B. 2.
C. 3.
D. 4.
Answer= 2
126. In which of the following access, the address is supplied?.
A. the first access.
B. the second access.
C. third access.
D. fourth access.
Answer= the first access
127. What type of timing is required for the burst interfaces?.
A. synchronous.
B. equal.
C. unequal.
D. symmetrical.
Answer= unequal
128. How can gate delays be reduced?.
A. synchronous memory.
B. asynchronous memory.
C. pseudo asynchronous memory.
D. symmetrical memory.
Answer= synchronous memory
129. In which memory does the burst interfaces act as a part of the cache?.
A. DRAM.
B. ROM.
C. SRAM.
D. Flash memory.
Answer= SRAM
130. Which of the following uses a wrap around burst interfacing?.
A. MC68030.
B. MC68040.
C. HyperBus.
D. US 5729504 A.
Answer= MC68040
131. Which of the following is a Motorola's protocol product?.
A. MCM62940.
B. Avalon.
C. Slave interfaces.
D. AXI slave interfaces.
Answer= MCM62940
132. Which of the following uses a linear line fill interfacing?.
A. MC68040.
B. MC68030.
C. US 74707 B2.
D. Hyper Bus.
Answer= MC68030
133. Which of the following protocol matches the Intel 80486?.
A. MCM62940.
B. MCM62486.
C. US 74707 B2.
D. Hyper Bus.
Answer= MCM62486
134. Which of the following protocol matches the MC68040?.
A. MCM62486.
B. US 5729504 A.
C. HyperBus.
D. MCM62940.
Answer= MCM62940
135. Which of the following is the biggest challenge in the cache memory design?.
A. delay.
B. size.
C. coherency.
D. memory access.
Answer= coherency
136. What arises when a copy of data is held both in the cache and in the main memory?.
A. stall data.
B. stale data.
C. stop data.
D. wait for the state.
Answer= stale data
137. In which writing scheme does all the data writes go through to main memory and update the system and cache?.
A. write-through.
B. write-back.
C. write buffering.
D. no caching of writing cycle.
Answer= write-through
138. In which writing scheme does the cache is updated but the main memory is not updated?.
A. write-through.
B. write-back.
C. no caching of writing cycle.
D. write buffering.
Answer= write-back
139. In which writing scheme does the cache is not updated?.
A. write-through.
B. write-back.
C. write buffering.
D. no caching of writing cycle.
Answer= no caching of writing cycle
140. Which writing mechanism forms the backbone of the bus snooping mechanism?.
A. write-back.
B. write-through.
C. no caching of write cycles.
D. write buffer.
Answer= no caching of write cycles
141. What is the main idea of the writing scheme in the cache memory?.
A. debugging.
B. accessing data.
C. bus snooping.
D. write-allocate.
Answer= bus snooping
142. In which scheme does the data write via a buffer to the main memory?.
A. write buffer.
B. write-back.
C. write-through.
D. no caching of the write cycle.
Answer= write buffer
143. Which of the following can allocate entries in the cache for any data that is written out?.
A. write-allocate cache.
B. read-allocate cache.
C. memory-allocate cache.
D. write cache.
Answer= write-allocate cache
144. Which of the following uses a bus snooping mechanism?.
A. MC88100.
B. 8086.
C. 8051.
D. 80286.
Answer= MC88100
145. What leads to the development of MESI and MEI protocol?.
A. cache size.
B. cache coherency.
C. bus snooping.
D. number of caches.
Answer= cache coherency
146. Which of the following is also known as Illinois protocol?.
A. MESI protocol.
B. MEI protocol.
C. Bus snooping.
D. Modified exclusive invalid.
Answer= MESI protocol
147. What does MESI stand for?.
A. modified exclusive stale invalid.
B. modified exclusive shared invalid.
C. modified exclusive system input.
D. modifies embedded shared invalid.
Answer= modified exclusive shared invalid
148. What does MEI stand for?.
A. modified embedded invalid.
B. modified embedded input.
C. modified exclusive invalid.
D. modified exclusive input.
Answer= modified exclusive invalid
149. Which protocol does MPC601 use?.
A. MESI protocol.
B. MEI protocol.
C. MOSI protocol.
D. MESIF protocol.
Answer= MESI protocol
150. The modified bit is also known as.
A. dead bit.
B. neat bit.
C. dirty bit.
D. invalid bit.
Answer= dirty bit
151. Which of the following have an 8 KB page?.
A. DEC Alpha.
B. ARM.
C. VAX.
D. PowerPC.
Answer= DEC Alpha
152. Which of the following address is seen by the memory unit?.
A. logical address.
B. physical address.
C. virtual address.
D. memory address.
Answer= physical address
153. Which of the following modes offers segmentation in the memory?.
A. virtual mode.
B. real mode.
C. protected mode.
D. memory mode.
Answer= protected mode
154. Which of the following is necessary for the address translation in the protected mode?.
A. descriptor.
B. paging.
C. segmentation.
D. memory.
Answer= descriptor
155. What does "G" in the descriptor entry describe?.
A. gain.
B. granularity.
C. gate voltage.
D. global descriptor.
Answer= granularity
156. How many types of tables are used by the processor in the protected mode?.
A. 1.
B. 2.
C. 3.
D. 4.
Answer= 2
157. What does the table indicator indicate when it is set to one?.
A. GDT.
B. LDT.
C. remains unchanged.
D. toggles with GTD and LTD.
Answer= LDT
158. What does GDTR stand for?.
A. global descriptor table register.
B. granularity descriptor table register.
C. gate register.
D. global direct table register.
Answer= global descriptor table register
159. What does PMMU stands for?.
A. protection mode memory management unit.
B. paged memory management unit.
C. physical memory management unit.
D. paged multiple management unit.
Answer= paged memory management unit
160. Which of the following support virtual memory?.
A. segmentation.
B. descriptor.
C. selector.
D. paging.
Answer= paging
161. What does DPL in the descriptor describes?.
A. descriptor page level.
B. descriptor privilege level.
C. direct page level.
D. direct page latch.
Answer= descriptor privilege level
162. What does "S" bit describe in a descriptor?.
A. descriptor type.
B. small type.
C. page type.
D. segmented type.
Answer= descriptor type
163. How many regions are created by the memory range in the ARM architecture?.
A. 4.
B. 8.
C. 16.
D. 32.
Answer= 8
164. How many bits does the memory region in the ARM memory protection unit have?.
A. 1.
B. 2.
C. 3.
D. 4.
Answer= 3
165. Which of the following uses a priority level for permitting data?.
A. ARM memory management unit.
B. ARM protection memory management unit.
C. Bus interface unit.
D. Execution unit.
Answer= ARM protection memory management unit
166. What type of bit in the ARM memory mimics to that of the protection unit of ARM management unit?.
A. permission bit.
B. buffer bit.
C. cacheable bit.
D. access permission bit.
Answer= permission bit
167. Which of the following bits are used to control the cache behaviour?.
A. cacheable bit.
B. buffer bit.
C. cacheable bit and buffer bit.
D. cacheable bit, buffer bit and permission access bit.
Answer= cacheable bit and buffer bit
168. Which of the following unit provides security to the processor?.
A. bus interface unit.
B. execution unit.
C. peripheral unit.
D. memory protection unit.
Answer= memory protection unit
169. Which of the following includes a tripped down memory management unit?.
A. memory protection unit.
B. memory real mode.
C. memory management unit.
D. bus interface unit.
Answer= memory protection unit
170. Which of the following can reduce the chip size?.
A. memory management unit.
B. execution unit.
C. memory protection unit.
D. bus interface unit.
Answer= memory protection unit
171. How does the memory management unit provide the protection?.
A. disables the address translation.
B. enables the address translation.
C. wait for the address translation.
D. remains unchanged.
Answer= disables the address translation
172. Which of the following is used to start a supervisor level?.
A. error signal.
B. default signal.
C. wait for the signal.
D. interrupt signal.
Answer= error signal
173. What happens when a task attempts to access memory outside its own address space?.
A. paging fault.
B. segmentation fault.
C. wait.
D. remains unchanged.
Answer= segmentation fault