Q1. Which transistor element is used in CMOS logic?.
A. FET.
B. MOSFET.
C. Bipolar.
D. Unijunction.
Answer= MOSFET
Q2. The greater the propagation delay, the ________..
A. lower the maximum freQncy.
B. higher the maximum freQncy.
C. maximum freQncy is unaffected.
D. minimum freQncy is unaffected.
Answer= lower the maximum freQncy
Q3. An open-drain gate is the CMOS counterpart of ________..
A. an open-collector TTL gate.
B. a tristate TTL gate.
C. a bipolar junction transistor.
D. an emitter-coupled logic gate.
Answer= an open-collector TTL gate
Q4. he nominal value of the dc supply voltage for TTL and CMOS is ________..
A. +3 V.
B. +5 V.
C. +9 V.
D. +12 V.
Answer= +5 V
Q5. Which logic family combines the advantages of CMOS and TTL?.
A. BiCMOS.
B. TTL/CMOS.
C. ECL.
D. TTL/MOS.
Answer= BiCMOS
Q6. The active switching element used in all TTL circuits is the ________..
A. bipolar junction transistor (BJT).
B. field-effect transistor (FET).
C. metal-oxide semiconductor field-effect transistor (MOSFET).
D. unijunction transistor (UJ).
Answer= bipolar junction transistor (BJT)
Q7. An open-collector output requires ________..
A. a pull-down resistor.
B. a pull-up resistor.
C. no output resistor.
D. an output resistor.
Answer= a pull-up resistor
Q8. Most TTL logic used today is some form of ________..
A. Schottky TTL.
B. tristate TTL.
C. low-power TTL.
D. open-collector TTL.
Answer= Schottky TTL
Q9. One output structure of a TTL gate is often referred to as a ________..
A. totem-pole arrangement.
B. diode arrangement.
C. JBT arrangement.
D. base, emitter, collector arrangement.
Answer= totem-pole arrangement
Q10. It is best not to leave unused TTL inputs unconnected (open) because of TTL's ________..
A. noise sensitivity.
B. low-current requirement.
C. open-collector outputs.
D. tristate construction.
Answer= noise sensitivity
Q11. Which is not an output state for tristate logic?.
A. HIGH.
B. LOW.
C. High-Z.
D. Low-Z.
Answer= Low-Z
Q12. TTL is alive and well, particularly in ________..
A. industrial applications.
B. educational applications.
C. military applications.
D. commercial applications.
Answer= educational applications
Q13. PMOS and NMOS circuits are used largely in ________..
A. MSI functions.
B. LSI functions.
C. diode functions.
D. TTL functions.
Answer= LSI functions
Q14. Which is not a precaution for handling CMOS?.
A. Devices should be placed with pins down on a grounded surface, such as a metal plate..
B. All tools, test equipment, and metal workbenches should be earth grounded..
C. CMOS devices should not be inserted into sockets or PC boards with the power on..
D. Wear wool clothes at all times..
Answer= Wear wool clothes at all times.
Q15. Which factor does not affect CMOS loading?.
A. Charging time associated with the output resistance of the driving gate.
B. Discharging time associated with the output resistance of the driving gate.
C. Output capacitance of the load gates.
D. Input capacitance of the load gates.
Answer= Output capacitance of the load gates
Q16. Which is not part of emitter-coupled logic (ECL)?.
A. Differential amplifier.
B. Bias circuit.
C. Emitter-follower circuit.
D. Totem-pole circuit.
Answer= Totem-pole circuit
Q17. Which of the following logic families has the highest maximum clock freQncy?.
A. S-TTL.
B. AS-TTL.
C. HS-TTL.
D. HCMOS.
Answer= AS-TTL
Q18. Logic circuits that are designated as buffers, drivers, or buffer/drivers are designed to have:.
A. a greater current/voltage capability than an ordinary logic circuit..
B. greater input current/voltage capability than an ordinary logic circuit..
C. a smaller output current/voltage capability than an ordinary logic..
D. greater input and output current/voltage capability than an ordinary logic circuit..
Answer= a greater current/voltage capability than an ordinary logic circuit.