1. The time taken to respond to an interrupt is known as.
A. interrupt delay.
B. interrupt time.
C. interrupt latency.
D. interrupt function.
Answer= interrupt latency
2. Into how many parts does the interrupt can split the software?.
A. 2.
B. 3.
C. 4.
D. 5.
Answer= 2
3. Which of the following allows the splitting of the software?.
A. wait statement.
B. ready.
C. interrupt.
D. acknowledgement.
Answer= interrupt
4. Which part of the software is transparent to the interrupt mechanism?.
A. background.
B. foreground.
C. both background and foreground.
D. lateral ground.
Answer= background
5. Which part of the software performs tasks in response to the interrupts?.
A. background.
B. foreground.
C. lateral ground.
D. both foreground and background.
Answer= foreground
6. In which of the following method does the code is written in a straight sence?.
A. method 1.
B. timing method.
C. sence method.
D. spaghetti method.
Answer= spaghetti method
7. Which factor depends on the number of times of polling the port while executing the task?.
A. data.
B. data transfer rate.
C. data size.
D. number of bits.
Answer= data transfer rate
8. Which of the following can improve the quality and the structure of a code?.
A. polling.
B. subroutine.
C. sential code.
D. concurrent code.
Answer= subroutine
9. Which of the following are asynchronous to the operation?.
A. interrupts.
B. software.
C. DMA.
D. memory.
Answer= interrupts
10. Which of the following can be used to create time-driven systems?.
A. memory.
B. input.
C. output.
D. interrupts.
Answer= interrupts
11. What does ISR stand for?.
A. interrupt standard routine.
B. interrupt service routine.
C. interrupt software routine.
D. interrupt synchronous routine.
Answer= interrupt service routine
12. Which can activate the ISR?.
A. interrupt.
B. function.
C. procedure.
D. structure.
Answer= interrupt
13. Which code is written as part of the ISR?.
A. data receive code.
B. sential code.
C. data transfer code.
D. concurrent code.
Answer= data transfer code
14. Which of the following uses clock edge to generate an interrupt?.
A. edge triggered.
B. level-triggered.
C. software interrupt.
D. nmi.
Answer= edge triggered
15. In which interrupt, the trigger is dependent on the logic level?.
A. edge triggered.
B. level-triggered.
C. software interrupt.
D. nmi.
Answer= level-triggered
16. At which point the processor will start to internally process the interrupt?.
A. interrupt pointer.
B. instruction pointer.
C. instruction boundary.
D. interrupt boundary.
Answer= instruction boundary
17. What does 80?�86 use to hold essential data?.
A. stack frame.
B. register.
C. internal register.
D. flag register.
Answer= stack frame
18. What does the RISC processor use to hold the data?.
A. flag register.
B. accumulator.
C. internal register.
D. stack register.
Answer= internal register
19. Which of the following is a stack-based processor?.
A. MC68000.
B. PowerPC.
C. ARM.
D. DEC Alpha.
Answer= MC68000
20. Which of the following is used to reduce the external memory cycle?.
A. internal hardware stack.
B. internal software stack.
C. external software stack.
D. internal register.
Answer= internal hardware stack
21. How many interrupt levels are supported in the MC68000?.
A. 2.
B. 3.
C. 4.
D. 7.
Answer= 7
22. How many interrupt pins are used in MC68000?.
A. 2.
B. 3.
C. 4.
D. 5.
Answer= 3
23. Which priority encoder is used in MC68000?.
A. 4-to-2 priority encoder.
B. LS148 7-to-3.
C. 2-to-4 priority encoder.
D. LS148 3-to-7.
Answer= LS148 7-to-3
24. Which of the following converts the seven external pins into a 3-bit binary code?.
A. priority encoder.
B. 4-to-2 priority encoder.
C. LS148 7-to-3.
D. 2-to-4 priority encoder.
Answer= LS148 7-to-3
25. Which of the following ensures the recognition of the interrupt?.
A. interrupt ready.
B. interrupt acknowledge.
C. interrupt terminal.
D. interrupt start.
Answer= interrupt acknowledge
26. Which of the following is raised to the interrupt level to prevent the multiple interrupt rest?.
A. internal interrupt mask.
B. external interrupt mask.
C. non-maskable interrupt.
D. software interrupt.
Answer= internal interrupt mask
27. Which of the following can be done to ensure that all interrupts are recognised?.
A. reset pin.
B. external ready pin.
C. handshaking.
D. acknowledgment.
Answer= handshaking
28. How many types of exceptions are associated with the asynchronous imprecise?.
A. 1.
B. 2.
C. 3.
D. 4.
Answer= 2
29. How is the internal registers and memories are reset?.
A. system reset.
B. memory reset.
C. peripheral reset.
D. software reset.
Answer= system reset
30. How is the machine check exception is taken in an asynchronous imprecise?.
A. ME bit.
B. EE bit.
C. FE0.
D. FE1.
Answer= ME bit
31. Which of the following are the exceptions associated with the asynchronous imprecise?.
A. decrementer interrupt.
B. machine check.
C. instruction dependent.
D. external interrupt.
Answer= machine check
32. Which of the following possesses an additional priority?.
A. asynchronous precise.
B. asynchronous imprecise.
C. synchronous precise.
D. synchronous imprecise.
Answer= synchronous precise
33. Which of the following has more priority?.
A. system reset.
B. machine check.
C. external interrupt.
D. decrementer interrupt.
Answer= system reset
34. Which bit controls the external interrupts and the decrementer exceptions?.
A. FE1.
B. FE0.
C. EE.
D. ME.
Answer= EE
35. Which bit controls the machine check exceptions?.
A. ME.
B. FE0.
C. FE1.
D. EE.
Answer= ME
36. Which bits control the floating point exceptions?.
A. EE.
B. FE0.
C. FE1.
D. both FE1 and FE2.
Answer= both FE1 and FE2
37. Which of the following is a 16 kbyte block?.
A. register.
B. vector table.
C. buffer.
D. lookaside buffer.
Answer= vector table
38. What does MSR stand for?.
A. machine state register.
B. machine software register.
C. minimum state register.
D. maximum state register.
Answer= machine state register
39. How many supervisor registers are associated with the exception mode?.
A. 2.
B. 3.
C. 4.
D. 5.
Answer= 2
40. What happens when an exception is completed?.
A. TRAP instruction executes.
B. SWI instruction executes.
C. RFI instruction executes.
D. terminal count increases.
Answer= RFI instruction executes
41. How many general types of exceptions are there?.
A. 2.
B. 3.
C. 6.
D. 4.
Answer= 4
42. In which of the exceptions does the external event causes the exception?.
A. synchronous exception.
B. asynchronous exception.
C. precise.
D. imprecise.
Answer= asynchronous exception
43. Which of the exceptions are usually a catastrophic failure?.
A. imprecise exception.
B. precise exception.
C. synchronous exception.
D. asynchronous exception.
Answer= imprecise exception
44. Which of the exceptions allows the system reset or memory fault?.
A. imprecise exception.
B. precise exception.
C. synchronous exception.
D. asynchronous exception.
Answer= imprecise exception
45. Which registers are used to determine the completion status?.
A. MSR.
B. flag register.
C. DSISR.
D. index register.
Answer= DSISR
46. Which of the following does not support PowerPC architecture?.
A. synchronous precise.
B. asynchronous precise.
C. synchronous imprecise.
D. asynchronous imprecise.
Answer= synchronous imprecise
47. Which exceptions are used in the PowerPC for floating point?.
A. synchronous imprecise.
B. asynchronous imprecise.
C. synchronous precise.
D. synchronous imprecise.
Answer= synchronous imprecise
48. Which exception is used in the external interrupts and decrementer-caused exceptions?.
A. synchronous precise.
B. asynchronous precise.
C. synchronous imprecise.
D. asynchronous imprecise.
Answer= asynchronous precise
49. Which exception can be masked by clearing the EE bit to zero in the MSR?.
A. synchronous imprecise.
B. synchronous precise.
C. asynchronous imprecise.
D. asynchronous precise.
Answer= asynchronous precise
50. Which interrupts are generated by the on-chip peripherals?.
A. internal.
B. external.
C. software.
D. hardware.
Answer= internal
51. Which of the following is the common method for connecting the peripheral to the processor?.
A. internal interrupts.
B. external interrupts.
C. software.
D. exception.
Answer= external interrupts
52. Which interrupt can make a change in the processor's mode?.
A. internal interrupt.
B. external interrupts.
C. exceptions.
D. software mode.
Answer= exceptions
53. How many exceptions does an MC68000 have?.
A. 256.
B. 128.
C. 90.
D. 70.
Answer= 90
54. Which interrupts allows a protected state?.
A. internal interrupt.
B. external interrupt.
C. software interrupt.
D. both internal and external interrupts.
Answer= software interrupt
55. How a software interrupt is created?.
A. instruction set.
B. sential code.
C. concurrent code.
D. porting.
Answer= instruction set
56. What does SWI stand for?.
A. standard interrupt instruction.
B. sential interrupt instruction.
C. software interrupt instruction.
D. system interrupt instruction.
Answer= software interrupt instruction
57. Which of the following use SWI as interrupt mechanism?.
A. PowerPC.
B. MC68000.
C. Z80.
D. IBM PC.
Answer= Z80
58. Which of the following supplies additional data to the software interrupt?.
A. internal interrupt.
B. external interrupt.
C. software interrupt.
D. nmi.
Answer= software interrupt
59. Which software interrupt is used in MC68000?.
A. Internal interrupt.
B. TRAP.
C. SWI.
D. NMI.
Answer= TRAP
60. Which of the following are accessible by the ISR in software interrupt mechanism?.
A. register.
B. interrupt.
C. nmi.
D. memory.
Answer= register
61. What allows the data protection in the software interrupt mechanism?.
A. Different mode.
B. Same mode.
C. SWI.
D. TRAP.
Answer= Different mode
62. What does NMI stand for?.
A. non-machine interrupt.
B. non-maskable interrupt.
C. non-massive interrupt.
D. non-memory interrupt.
Answer= non-maskable interrupt
63. Which NMI is used in the IBM PC?.
A. SWI.
B. TRAP.
C. 80?�86 NMI.
D. Maskable interrupt.
Answer= 80?�86 NMI
64. Which can be used to pass the status information to the calling software in the software interrupt mechanism?.
A. register.
B. memory.
C. flag.
D. nmi.
Answer= register
65. Which processors use fast interrupts?.
A. DSP processor.
B. RISC processor.
C. CISC processor.
D. Harvard processor.
Answer= DSP processor
66. Which interrupts generate fast interrupt exception?.
A. internal interrupt.
B. external interrupt.
C. software interrupt.
D. hardware interrupt.
Answer= external interrupt
67. What is the disadvantage of the fast interrupts?.
A. stack frame.
B. delay.
C. size of routine.
D. low speed.
Answer= size of routine
68. Which of the following does not have a stack frame building?.
A. hardware interrupt.
B. software interrupt.
C. non-maskable interrupt.
D. fast interrupt.
Answer= fast interrupt
69. What is programmed to generate a two instruction fast interrupt?.
A. software.
B. application.
C. timer.
D. sensor.
Answer= timer
70. Which of the following can auto increment the register R1?.
A. SCI timer.
B. interrupt.
C. software interrupt.
D. non-maskable interrupt.
Answer= SCI timer
71. Which of the following forces a standard service routine?.
A. READY interrupt.
B. IRQA interrupt.
C. NMI.
D. software interrupt.
Answer= IRQA interrupt
72. Which of the following can be used as a reset button?.
A. NMI.
B. internal interrupt.
C. external interrupt.
D. software interrupt.
Answer= NMI
73. Which of the following is connected to a fault detection circuit?.
A. internal interrupt.
B. external interrupt.
C. NMI.
D. software interrupt.
Answer= NMI