1. POP operation
a. decrements SP
b. increments SP
c. decrements SS
d. increments SS
Ans- b. increments SP
2. PUSH operation
a. decrements SP
b. increments SP
c. decrements SS
d. increments SS
Ans- a. decrements SP
3. The stack segment register contains
a. address of the stack segment
b. base address of the stack segment
c. pointer address of the stack segment
d. data in the stack segment
Ans- b. base address of the stack segment
4. The stack pointer register contains
a. address of the stack segment
b. pointer address of the stack segment
c. offset of address of stack segment
d. data present in the stack segment
Ans- c. offset of address of stack segment
5. With the trailing edge of the LOCK (active low), the INTA (active low) goes low and remains in it for
a. 0 clock cycle
b. 1 clock cycle
c. 2 clock cycles
d. 3 clock cycles
Ans- c. 2 clock cycles
6. If the pin LOCK (active low base) is low at the trailing edge of the first ALE pulse, then till the start of the next machine cycle, the pin LOCK (active low) is
a. low
b. high
c. low or high
d. none
Ans- a. low
7. Once the processor responds to an INTR signal, the IF is automatically
a. set
b. reset
c. high
d. low
Ans- b. reset
8. The status of the pending interrupts is checked at
a. the end of main program
b. the end of all the interrupts executed
c. the beginning of every interrupt
d. the end of each instruction cycle
Ans- d. the end of each instruction cycle
9. For the INTR signal, to be responded to in the next instruction cycle, it must go ____ in the last clock cycle of the current instruction
a. high
b. low
c. high or low
d. unchanged
Ans- a. high
10. The INTR signal can be masked by resetting the
a. TRAP flag
b. INTERRUPT flag
c. MASK flag
d. DIRECTION flag
Ans- b. INTERRUPT flag