Medium Scale Integrated Logic Circuit in Digital Logic Design MCQs

Medium Scale Integrated Logic Circuit in Digital Logic Design MCQs

 Q1. A 16-input multiplexer is to be used to perform parallel-to-serial data conversion. Which of the following counters would be required to provide the data select inputs?. 

A. MOD 8. 

B. MOD 16. 

C. MOD 4. 

D. MOD 2. 

Answer= MOD 16


Q2. How is the number one (1) indicated on the outputs of a 7447 BCD-to-seven-segment code converter?. 

A. Segment a is active.. 

B. Segment b is active.. 

C. Segments a and b are active.. 

D. Segments b and c are active.. 

Answer= Segments b and c are active.


Q3. The IEEE/ANSI symbol for a decoder has the internal designation bcd/dec. This means the decoder is a:. 

A. decimal-to-BCD decoder with ten inputs and four outputs.. 

B. BCD-to-decimal decoder with ten inputs and four outputs.. 

C. decimal-to-BCD decoder with four inputs and ten outputs.. 

D. BCD-to-decimal decoder with four inputs and ten outputs.. 

Answer= BCD-to-decimal decoder with four inputs and ten outputs.


Q4. Multiplexing of digital signals is usually required when:. 

A. moving data internally within a microprocessor.. 

B. moving data between memory and storage registers in a microprocessor.. 

C. moving data over long distance transmission lines.. 

D. moving data internally within a microprocessor or between memory and storage registers.. 

Answer= moving data over long distance transmission lines.


Q5. Which is the decimal number for the BCD number, 10110110?. 

A. 182. 

B. 36. 

C. 116. 

D. 10110110 is not a valid BCD number.. 

Answer= 10110110 is not a valid BCD number.


Q6. In an AHDL BCD to binary code converter, how is multiplication by 10 accomplished?. 

A. By using the shifting of bits. 

B. By using the library multiplication function. 

C. By using integer types. 

D. By using the multiplication operator. 

Answer= By using the shifting of bits


Q7. What is the HDL key issue in the design of the MUX and DEMUX?. 

A. Having the MUX and DEMUX part of the library. 

B. Using the case statement in the process. 

C. Describing the functions. 

D. Assigning signals under certain conditions. 

Answer= Assigning signals under certain conditions


Q8. Why are control inputs included in an HDL magnitude comparator?. 

A. For cascading the chips. 

B. For control signal input. 

C. For signal control. 

D. For internal interconnections. 

Answer= For cascading the chips


Q9. What VHDL techniQs are used to describe a priority encoder?. 

A. Integer outputs and priority coding. 

B. Signal outputs and priority coding. 

C. Tristate outputs and priority coding. 

D. Variables and priority coding. 

Answer= Tristate outputs and priority coding


Q10. What is an important attribute of the conditional signal assignment statement?. 

A. Its tristate outputs. 

B. Its seQntial evaluation. 

C. Its use of library components. 

D. Its fast activation times. 

Answer= Its seQntial evaluation


Q11. What is the purpose of a decoder's inputs?. 

A. To allow the decoder to respond to the inputs to activate the correct output gate.. 

B. To disable the decoder outputs so that all outputs will be inactive.. 

C. To disable the inputs and activate all outputs.. 

D. To allow the decoder to respond to the inputs to activate the correct output gate, and to disable the inputs and activate all outputs.. 

Answer= To allow the decoder to respond to the inputs to activate the correct output gate, and to disable the inputs and activate all outputs.


Q12. In a freQncy counter, what happens at high freQncies when the sampling interval is too long?. 

A. The counter works fine.. 

B. The counter undercounts the freQncy.. 

C. The measurement is less precise.. 

D. The counter overflows.. 

Answer= The counter overflows.


Q13. In the digital clock project, when does the PM indicator go high?. 

A. Never. 

B. Going from 11:59:59 to 12:00:00. 

C. Going from 12:59:59 to 01:00:00. 

D. On the falling edge of the clock after enable goes high. 

Answer= Going from 11:59:59 to 12:00:00

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