1. If at a time A0 and BHE(active low) both are zero then, the chip(s) selected will be
a. RAM
b. ROM
c. RAM and ROM
d. ONLY RAM
Ans- c. RAM and ROM
2. If (address line) A0=0 then, the status of address and memory are
a. address is even and memory is in ROM
b. address is odd and memory is in ROM
c. address is even and memory is in RAM
d. address is odd and memory is in RAM
Ans- c. address is even and memory is in RAM
3. To obtain 16-bit data bus width, the two 4K*8 chips of RAM and ROM are arranged in
a. parallel
b. serial
c. both serial and parallel
d. neither serial nor parallel
Ans- a. parallel
4. In most of the cases, the method used for decoding that may be used to minimise the required hardware is
a. absolute decoding
b. non-linear decoding
c. linear decoding
d. none
Ans- c. linear decoding
5. In static memory, the lower 8-bit bank of an available 16-bit memory chip is called
a. lower address memory bank
b. even address memory bank
c. static lower memory bank
d. odd address memory bank
Ans- b. even address memory bank
6. In static memory, the upper 8-bit bank of an available 16-bit memory chip is called
a. upper address memory bank
b. even address memory bank
c. static upper memory
d. odd address memory bank
Ans- d. odd address memory bank
7. If the microprocessor has 10 address lines, then the number of memory locations it is able to address is
a. 512
b. 1024
c. 2048
d. none
Ans- b. 1024
8. To address a memory location out of N memory locations, the number of address lines required is
a. log N (to the base 2)
b. log N (to the base 10)
c. log N (to the base e)
d. log (2N) (to the base e)
Ans- a. log N (to the base 2)
9. If a location is selected, then all the bits in it are accessible using a group of conductors called
a. control bus
b. address bus
c. data bus
d. either address bus or data bus
Ans- c. data bus
10. The semiconductor memories are organised as ____ dimension(s) of array of memory locations.
a. one dimensional
b. two dimensional
c. three dimensional
d. none
Ans- b. two dimensional